mirror of
https://github.com/infiniteCable2/panda.git
synced 2026-02-19 17:53:53 +08:00
7d93e5a202
* Let refactoring begin! * Fix pedal build * Fix pedal safety tests * Forgot few TIM2 instances * Try this way with misra * More misras... * More misras... * Still fighting with misra blindfolded * Almost got it! * Last misra error.. * Last misra error.. * Misra works locally.. * Maybe this? * Looks like it was cppcheck bug, revert changes * Suggested changes and reverts * File structure change * revert includes * remove spaces * remove timer delay * endings * more typing * rename early to early_initialization * Remove delay_us * Revert RTC default values * Revert initialization sequence * Fix quotes * Revert * Return TIM6EN * Alias slow timer to TICK_TIMER * Refactor files structure * Remove definition of PANDA * Abstract timers * Fix include * tick_timer_init * Split usb driver * Move LL stuff: adc * Move LL stuff: usb * Fix include again... * Will check pedal builds also locally.. * Move LL stuff: CAN * Move LL stuff: clock * Rename common to peripherals and move * Move board HAL * Change include, not needed for pedal * llgpio to gpio and new lines fix * remove board_has_relay, not used * Remove board_functions.h and add to board struct * Move include * Fk MISRA... * has_onboard_gmlan to has_hw_gmlan * Typos * Move board_declarations include * Shuffle * More abstraction * fix paths, fix cppcheck test * Fix for pedal build with USB
57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
#define PWM_COUNTER_OVERFLOW 2000U // To get ~50kHz
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// TODO: Implement for 32-bit timers
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void pwm_init(TIM_TypeDef *TIM, uint8_t channel){
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// Enable timer and auto-reload
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register_set(&(TIM->CR1), TIM_CR1_CEN | TIM_CR1_ARPE, 0x3FU);
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// Set channel as PWM mode 1 and enable output
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switch(channel){
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case 1U:
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register_set_bits(&(TIM->CCMR1), (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE));
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register_set_bits(&(TIM->CCER), TIM_CCER_CC1E);
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break;
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case 2U:
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register_set_bits(&(TIM->CCMR1), (TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE));
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register_set_bits(&(TIM->CCER), TIM_CCER_CC2E);
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break;
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case 3U:
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register_set_bits(&(TIM->CCMR2), (TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE));
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register_set_bits(&(TIM->CCER), TIM_CCER_CC3E);
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break;
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case 4U:
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register_set_bits(&(TIM->CCMR2), (TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE));
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register_set_bits(&(TIM->CCER), TIM_CCER_CC4E);
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break;
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default:
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break;
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}
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// Set max counter value
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register_set(&(TIM->ARR), PWM_COUNTER_OVERFLOW, 0xFFFFU);
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// Update registers and clear counter
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TIM->EGR |= TIM_EGR_UG;
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}
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void pwm_set(TIM_TypeDef *TIM, uint8_t channel, uint8_t percentage){
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uint16_t comp_value = (((uint16_t) percentage * PWM_COUNTER_OVERFLOW) / 100U);
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switch(channel){
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case 1U:
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register_set(&(TIM->CCR1), comp_value, 0xFFFFU);
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break;
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case 2U:
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register_set(&(TIM->CCR2), comp_value, 0xFFFFU);
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break;
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case 3U:
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register_set(&(TIM->CCR3), comp_value, 0xFFFFU);
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break;
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case 4U:
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register_set(&(TIM->CCR4), comp_value, 0xFFFFU);
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break;
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default:
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break;
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}
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}
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