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enable misra-c2012-12.2 (#1824) 

* enable misra-c2012-12.2

* refactor: use 1UL in all FAULT defs
This commit is contained in:
Ruben Medina 2024-01-20 16:19:34 -08:00 committed by GitHub
parent ced1fb3dee
commit 229e8bb3a5
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
11 changed files with 56 additions and 57 deletions
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6
board/drivers/gmlan_alt.h
View File

@ -95,7 +95,7 @@ int get_bit_message(char *out, CANPacket_t *to_bang) {
// extended identifier
len = append_int(pkt, len, GET_ADDR(to_bang) >> 18, 11); // Identifier
len = append_int(pkt, len, 3, 2); // SRR+IDE
len = append_int(pkt, len, (GET_ADDR(to_bang)) & ((1U << 18) - 1U), 18); // Identifier
len = append_int(pkt, len, (GET_ADDR(to_bang)) & ((1UL << 18) - 1U), 18); // Identifier
len = append_int(pkt, len, 0, 3); // RTR+r1+r0
} else {
// standard identifier
@ -175,9 +175,9 @@ void reset_gmlan_switch_timeout(void) {
void set_bitbanged_gmlan(int val) {
if (val != 0) {
register_set_bits(&(GPIOB->ODR), (1U << 13));
register_set_bits(&(GPIOB->ODR), (1UL << 13));
} else {
register_clear_bits(&(GPIOB->ODR), (1U << 13));
register_clear_bits(&(GPIOB->ODR), (1UL << 13));
}
}

8
board/drivers/gpio.h
View File

@ -27,9 +27,9 @@ void set_gpio_mode(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int mode) {
void set_gpio_output(GPIO_TypeDef *GPIO, unsigned int pin, bool enabled) {
ENTER_CRITICAL();
if (enabled) {
register_set_bits(&(GPIO->ODR), (1U << pin));
register_set_bits(&(GPIO->ODR), (1UL << pin));
} else {
register_clear_bits(&(GPIO->ODR), (1U << pin));
register_clear_bits(&(GPIO->ODR), (1UL << pin));
}
set_gpio_mode(GPIO, pin, MODE_OUTPUT);
EXIT_CRITICAL();
@ -38,7 +38,7 @@ void set_gpio_output(GPIO_TypeDef *GPIO, unsigned int pin, bool enabled) {
void set_gpio_output_type(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int output_type){
ENTER_CRITICAL();
if(output_type == OUTPUT_TYPE_OPEN_DRAIN) {
register_set_bits(&(GPIO->OTYPER), (1U << pin));
register_set_bits(&(GPIO->OTYPER), (1UL << pin));
} else {
register_clear_bits(&(GPIO->OTYPER), (1U << pin));
}
@ -65,7 +65,7 @@ void set_gpio_pullup(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int mode) {
}
int get_gpio_input(GPIO_TypeDef *GPIO, unsigned int pin) {
return (GPIO->IDR & (1U << pin)) == (1U << pin);
return (GPIO->IDR & (1UL << pin)) == (1UL << pin);
}
void gpio_set_all_output(const gpio_t *pins, uint8_t num_pins, bool enabled) {

24
board/drivers/usb.h
View File

@ -104,7 +104,7 @@ uint8_t resp[USBPACKET_MAX_SIZE];
// Convert machine byte order to USB byte order
#define TOUSBORDER(num)\
((num) & 0xFFU), (((num) >> 8) & 0xFFU)
((num) & 0xFFU), (((uint16_t)(num) >> 8) & 0xFFU)
// take in string length and return the first 2 bytes of a string descriptor
#define STRING_DESCRIPTOR_HEADER(size)\
@ -447,10 +447,10 @@ void usb_reset(void) {
USBx->GRXFSIZ = 0x40;
// 0x100 to offset past GRXFSIZ
USBx->DIEPTXF0_HNPTXFSIZ = (0x40U << 16) | 0x40U;
USBx->DIEPTXF0_HNPTXFSIZ = (0x40UL << 16) | 0x40U;
// EP1, massive
USBx->DIEPTXF[0] = (0x40U << 16) | 0x80U;
USBx->DIEPTXF[0] = (0x40UL << 16) | 0x80U;
// flush TX fifo
USBx->GRSTCTL = USB_OTG_GRSTCTL_TXFFLSH | USB_OTG_GRSTCTL_TXFNUM_4;
@ -463,7 +463,7 @@ void usb_reset(void) {
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
// ready to receive setup packets
USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)) | (3U << 3);
USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (3U << 3);
}
char to_hex_char(int a) {
@ -490,17 +490,17 @@ void usb_setup(void) {
switch (setup.b.bRequest) {
case USB_REQ_SET_CONFIGURATION:
// enable other endpoints, has to be here?
USBx_INEP(1)->DIEPCTL = (0x40U & USB_OTG_DIEPCTL_MPSIZ) | (2U << 18) | (1U << 22) |
USBx_INEP(1)->DIEPCTL = (0x40U & USB_OTG_DIEPCTL_MPSIZ) | (2UL << 18) | (1UL << 22) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_USBAEP;
USBx_INEP(1)->DIEPINT = 0xFF;
USBx_OUTEP(2)->DOEPTSIZ = (1U << 19) | 0x40U;
USBx_OUTEP(2)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2U << 18) |
USBx_OUTEP(2)->DOEPTSIZ = (1UL << 19) | 0x40U;
USBx_OUTEP(2)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) |
USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP;
USBx_OUTEP(2)->DOEPINT = 0xFF;
USBx_OUTEP(3)->DOEPTSIZ = (32U << 19) | 0x800U;
USBx_OUTEP(3)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2U << 18) |
USBx_OUTEP(3)->DOEPTSIZ = (32UL << 19) | 0x800U;
USBx_OUTEP(3)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) |
USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP;
USBx_OUTEP(3)->DOEPINT = 0xFF;
@ -802,7 +802,7 @@ void usb_irqhandler(void) {
#ifdef DEBUG_USB
print(" OUT2 PACKET XFRC\n");
#endif
USBx_OUTEP(2)->DOEPTSIZ = (1U << 19) | 0x40U;
USBx_OUTEP(2)->DOEPTSIZ = (1UL << 19) | 0x40U;
USBx_OUTEP(2)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
}
@ -833,7 +833,7 @@ void usb_irqhandler(void) {
if ((USBx_OUTEP(0)->DOEPINT & USB_OTG_DIEPINT_XFRC) != 0) {
// ready for next packet
USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)) | (1U << 3);
USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (1U << 3);
}
// respond to setup packets
@ -933,7 +933,7 @@ void usb_irqhandler(void) {
void can_tx_comms_resume_usb(void) {
ENTER_CRITICAL();
if (!outep3_processing && (USBx_OUTEP(3)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) != 0) {
USBx_OUTEP(3)->DOEPTSIZ = (32U << 19) | 0x800U;
USBx_OUTEP(3)->DOEPTSIZ = (32UL << 19) | 0x800U;
USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
}
EXIT_CRITICAL();

54
board/faults.h
View File

@ -3,33 +3,33 @@
#define FAULT_STATUS_PERMANENT 2U
// Fault types, matches cereal.log.PandaState.FaultType
#define FAULT_RELAY_MALFUNCTION (1U << 0)
#define FAULT_UNUSED_INTERRUPT_HANDLED (1U << 1)
#define FAULT_INTERRUPT_RATE_CAN_1 (1U << 2)
#define FAULT_INTERRUPT_RATE_CAN_2 (1U << 3)
#define FAULT_INTERRUPT_RATE_CAN_3 (1U << 4)
#define FAULT_INTERRUPT_RATE_TACH (1U << 5)
#define FAULT_INTERRUPT_RATE_GMLAN (1U << 6)
#define FAULT_INTERRUPT_RATE_INTERRUPTS (1U << 7)
#define FAULT_INTERRUPT_RATE_SPI_DMA (1U << 8)
#define FAULT_INTERRUPT_RATE_SPI_CS (1U << 9)
#define FAULT_INTERRUPT_RATE_UART_1 (1U << 10)
#define FAULT_INTERRUPT_RATE_UART_2 (1U << 11)
#define FAULT_INTERRUPT_RATE_UART_3 (1U << 12)
#define FAULT_INTERRUPT_RATE_UART_5 (1U << 13)
#define FAULT_INTERRUPT_RATE_UART_DMA (1U << 14)
#define FAULT_INTERRUPT_RATE_USB (1U << 15)
#define FAULT_INTERRUPT_RATE_TIM1 (1U << 16)
#define FAULT_INTERRUPT_RATE_TIM3 (1U << 17)
#define FAULT_REGISTER_DIVERGENT (1U << 18)
#define FAULT_INTERRUPT_RATE_KLINE_INIT (1U << 19)
#define FAULT_INTERRUPT_RATE_CLOCK_SOURCE (1U << 20)
#define FAULT_INTERRUPT_RATE_TICK (1U << 21)
#define FAULT_INTERRUPT_RATE_EXTI (1U << 22)
#define FAULT_INTERRUPT_RATE_SPI (1U << 23)
#define FAULT_INTERRUPT_RATE_UART_7 (1U << 24)
#define FAULT_SIREN_MALFUNCTION (1U << 25)
#define FAULT_HEARTBEAT_LOOP_WATCHDOG (1U << 26)
#define FAULT_RELAY_MALFUNCTION (1UL << 0)
#define FAULT_UNUSED_INTERRUPT_HANDLED (1UL << 1)
#define FAULT_INTERRUPT_RATE_CAN_1 (1UL << 2)
#define FAULT_INTERRUPT_RATE_CAN_2 (1UL << 3)
#define FAULT_INTERRUPT_RATE_CAN_3 (1UL << 4)
#define FAULT_INTERRUPT_RATE_TACH (1UL << 5)
#define FAULT_INTERRUPT_RATE_GMLAN (1UL << 6)
#define FAULT_INTERRUPT_RATE_INTERRUPTS (1UL << 7)
#define FAULT_INTERRUPT_RATE_SPI_DMA (1UL << 8)
#define FAULT_INTERRUPT_RATE_SPI_CS (1UL << 9)
#define FAULT_INTERRUPT_RATE_UART_1 (1UL << 10)
#define FAULT_INTERRUPT_RATE_UART_2 (1UL << 11)
#define FAULT_INTERRUPT_RATE_UART_3 (1UL << 12)
#define FAULT_INTERRUPT_RATE_UART_5 (1UL << 13)
#define FAULT_INTERRUPT_RATE_UART_DMA (1UL << 14)
#define FAULT_INTERRUPT_RATE_USB (1UL << 15)
#define FAULT_INTERRUPT_RATE_TIM1 (1UL << 16)
#define FAULT_INTERRUPT_RATE_TIM3 (1UL << 17)
#define FAULT_REGISTER_DIVERGENT (1UL << 18)
#define FAULT_INTERRUPT_RATE_KLINE_INIT (1UL << 19)
#define FAULT_INTERRUPT_RATE_CLOCK_SOURCE (1UL << 20)
#define FAULT_INTERRUPT_RATE_TICK (1UL << 21)
#define FAULT_INTERRUPT_RATE_EXTI (1UL << 22)
#define FAULT_INTERRUPT_RATE_SPI (1UL << 23)
#define FAULT_INTERRUPT_RATE_UART_7 (1UL << 24)
#define FAULT_SIREN_MALFUNCTION (1UL << 25)
#define FAULT_HEARTBEAT_LOOP_WATCHDOG (1UL << 26)
// Permanent faults
#define PERMANENT_FAULTS 0U

2
board/pedal/main.c
View File

@ -92,7 +92,7 @@ int comms_control_handler(ControlPacket_t *req, uint8_t *resp) {
// addresses to be used on CAN
#define CAN_GAS_INPUT 0x200
#define CAN_GAS_OUTPUT 0x201U
#define CAN_GAS_OUTPUT 0x201UL
#define CAN_GAS_SIZE 6
#define COUNTER_CYCLE 0xFU

10
board/safety/safety_toyota.h
View File

@ -86,11 +86,11 @@ RxCheck toyota_lta_interceptor_rx_checks[] = {
// safety param flags
// first byte is for EPS factor, second is for flags
const uint32_t TOYOTA_PARAM_OFFSET = 8U;
const uint32_t TOYOTA_EPS_FACTOR = (1U << TOYOTA_PARAM_OFFSET) - 1U;
const uint32_t TOYOTA_PARAM_ALT_BRAKE = 1U << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_STOCK_LONGITUDINAL = 2U << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_LTA = 4U << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_GAS_INTERCEPTOR = 8U << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_EPS_FACTOR = (1UL << TOYOTA_PARAM_OFFSET) - 1U;
const uint32_t TOYOTA_PARAM_ALT_BRAKE = 1UL << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_STOCK_LONGITUDINAL = 2UL << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_LTA = 4UL << TOYOTA_PARAM_OFFSET;
const uint32_t TOYOTA_PARAM_GAS_INTERCEPTOR = 8UL << TOYOTA_PARAM_OFFSET;
bool toyota_alt_brake = false;
bool toyota_stock_longitudinal = false;

2
board/stm32fx/llbxcan.h
View File

@ -140,7 +140,7 @@ bool llcan_init(CAN_TypeDef *CANx) {
CANx->sFilterRegister[0].FR2 = 0U;
CANx->sFilterRegister[14].FR1 = 0U;
CANx->sFilterRegister[14].FR2 = 0U;
CANx->FA1R |= 1U | (1U << 14);
CANx->FA1R |= 1U | (1UL << 14);
// Exit init mode, do not wait
register_clear_bits(&(CANx->FMR), CAN_FMR_FINIT);

2
board/stm32fx/llusb.h
View File

@ -7,7 +7,7 @@ USB_OTG_GlobalTypeDef *USBx = USB_OTG_FS;
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
#define USBD_FS_TRDT_VALUE 5U
#define USBD_FS_TRDT_VALUE 5UL
#define USB_OTG_SPEED_FULL 3

2
board/stm32h7/lldac.h
View File

@ -28,7 +28,7 @@ void dac_init(DAC_TypeDef *dac, uint8_t channel, bool dma) {
// Set channel 1 value, in mV
void dac_set(DAC_TypeDef *dac, uint8_t channel, uint32_t value) {
uint32_t raw_val = MAX(MIN(value * (1U << 8U) / 3300U, (1U << 8U)), 0U);
uint32_t raw_val = MAX(MIN(value * (1UL << 8U) / 3300U, (1UL << 8U)), 0U);
switch(channel) {
case 1:
register_set(&dac->DHR8R1, raw_val, 0xFFU);

2
board/stm32h7/llusb.h
View File

@ -7,7 +7,7 @@ USB_OTG_GlobalTypeDef *USBx = USB_OTG_HS;
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
#define USBD_FS_TRDT_VALUE 6U
#define USBD_FS_TRDT_VALUE 6UL
#define USB_OTG_SPEED_FULL 3U
#define DCFG_FRAME_INTERVAL_80 0U

1
tests/misra/suppressions.txt
View File

@ -30,6 +30,5 @@ misra-c2012-8.4
misra-c2012-10.6
misra-c2012-10.3
misra-c2012-10.5
misra-c2012-12.2
misra-c2012-17.3
misra-c2012-21.15