mirror of https://github.com/commaai/panda.git
refactor SPI and make flasher reliable
This commit is contained in:
Firmware Batman
parent
a2523f2d3a
commit
0a5a8ab5ec
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@ -12,9 +12,6 @@
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#include "libc.h"
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#include "gpio.h"
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void spi_cb_rx(uint8_t *data, int len) {};
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#include "drivers/drivers.h"
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#include "drivers/spi.h"
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@ -3,6 +3,7 @@
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//#define DEBUG
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//#define DEBUG_USB
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//#define DEBUG_SPI
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#ifdef STM32F4
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#define PANDA
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@ -70,8 +70,7 @@ void timer_init(TIM_TypeDef *TIM, int psc);
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// IRQs: DMA2_Stream2, DMA2_Stream3, EXTI4
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void spi_init();
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void spi_cb_rx(uint8_t *data, int len);
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void spi_tx_dma(void *addr, int len);
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int spi_cb_rx(uint8_t *data, int len, uint8_t *data_out);
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// ********************* CAN *********************
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@ -17,6 +17,10 @@ void spi_init() {
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NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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//NVIC_EnableIRQ(SPI1_IRQn);
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// reset handshake back to pull up
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0;
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// setup interrupt on falling edge of SPI enable (on PA4)
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SYSCFG->EXTICR[2] = SYSCFG_EXTICR2_EXTI4_PA;
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EXTI->IMR = (1 << 4);
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@ -39,6 +43,12 @@ void spi_tx_dma(void *addr, int len) {
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DMA2_Stream3->CR |= DMA_SxCR_TCIE;
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SPI1->CR2 |= SPI_CR2_TXDMAEN;
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// signal data is ready by driving low
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// esp must be configured as input by this point
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->MODER |= GPIO_MODER_MODER0_0;
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GPIOB->ODR &= ~(GPIO_ODR_ODR_0);
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}
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void spi_rx_dma(void *addr, int len) {
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@ -64,11 +74,22 @@ void spi_rx_dma(void *addr, int len) {
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// ***************************** SPI IRQs *****************************
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// can't go on the stack cause it's DMAed
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uint8_t spi_tx_buf[0x44];
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// SPI RX
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void DMA2_Stream2_IRQHandler(void) {
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// ack
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DMA2->LIFCR = DMA_LIFCR_CTCIF2;
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spi_cb_rx(spi_buf, 0x13);
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int *resp_len = (int*)spi_tx_buf;
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memset(spi_tx_buf, 0xaa, 0x44);
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*resp_len = spi_cb_rx(spi_buf, 0x13, spi_tx_buf+4);
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#ifdef DEBUG_SPI
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puts("SPI write: ");
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puth(*resp_len);
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puts("\n");
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#endif
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spi_tx_dma(spi_tx_buf, *resp_len + 4);
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}
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// SPI TX
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@ -76,6 +97,10 @@ void DMA2_Stream3_IRQHandler(void) {
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// ack
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DMA2->LIFCR = DMA_LIFCR_CTCIF3;
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#ifdef DEBUG_SPI
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puts("SPI handshake\n");
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#endif
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// reset handshake back to pull up
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0;
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27
board/main.c
27
board/main.c
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@ -358,25 +358,20 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, int hardwired) {
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}
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#ifdef PANDA
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// can't go on the stack cause it's DMAed
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uint8_t spi_tx_buf[0x44];
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void spi_cb_rx(uint8_t *data, int len) {
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memset(spi_tx_buf, 0xaa, 0x44);
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int spi_cb_rx(uint8_t *data, int len, uint8_t *data_out) {
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// data[0] = endpoint
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// data[2] = length
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// data[4:] = data
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int *resp_len = (int*)spi_tx_buf;
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*resp_len = 0;
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int resp_len = 0;
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switch (data[0]) {
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case 0:
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// control transfer
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*resp_len = usb_cb_control_msg((USB_Setup_TypeDef *)(data+4), spi_tx_buf+4, 0);
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resp_len = usb_cb_control_msg((USB_Setup_TypeDef *)(data+4), data_out, 0);
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break;
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case 1:
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// ep 1, read
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*resp_len = usb_cb_ep1_in(spi_tx_buf+4, 0x40, 0);
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resp_len = usb_cb_ep1_in(data_out, 0x40, 0);
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break;
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case 2:
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// ep 2, send serial
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@ -387,18 +382,12 @@ void spi_cb_rx(uint8_t *data, int len) {
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usb_cb_ep3_out(data+4, data[2], 0);
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break;
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}
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spi_tx_dma(spi_tx_buf, 0x44);
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// signal data is ready by driving low
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// esp must be configured as input by this point
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->MODER |= GPIO_MODER_MODER0_0;
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GPIOB->ODR &= ~(GPIO_ODR_ODR_0);
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return resp_len;
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}
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#else
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void spi_cb_rx(uint8_t *data, int len) {};
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int spi_cb_rx(uint8_t *data, int len) { return 0; };
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#endif
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@ -460,7 +449,7 @@ int main() {
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// set PWM
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fan_init();
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fan_set_speed(65535);
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fan_set_speed(0);
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puts("**** INTERRUPTS ON ****\n");
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@ -1,27 +1,83 @@
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/*void lock_bootloader() {
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if (FLASH->OPTCR & FLASH_OPTCR_nWRP_0) {
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// can't go on the stack cause it's DMAed
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uint8_t spi_tx_buf[0x44];
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// write protect the bootloader
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FLASH->OPTCR &= ~FLASH_OPTCR_nWRP_0;
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uint32_t *prog_ptr;
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int unlocked = 0;
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// OPT program
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FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
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int spi_cb_rx(uint8_t *data, int len, uint8_t *data_out) {
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// get serial number even in bootstub mode
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if (memcmp("\x00\x00\x00\x00\x40\xD0\x00\x00\x00\x00\x20\x00", data, 0xC) == 0) {
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memcpy(data_out, (void *)0x1fff79e0, 0x20);
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return 0x20;
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}
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// flasher mode
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if (data[0] == (0xff^data[1]) &&
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data[2] == (0xff^data[3])) {
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int sec;
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memset(data_out, 0, 4);
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memcpy(data_out+4, "\xde\xad\xd0\x0d", 4);
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data_out[0] = 0xff;
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data_out[2] = data[0];
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data_out[3] = data[1];
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switch (data[0]) {
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case 0xf:
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// echo
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data_out[1] = 0xff;
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break;
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case 0x10:
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// unlock flash
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if (FLASH->CR & FLASH_CR_LOCK) {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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data_out[1] = 0xff;
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}
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set_led(LED_GREEN, 1);
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unlocked = 1;
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prog_ptr = (uint32_t *)0x8004000;
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break;
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case 0x11:
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// erase
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sec = data[2] & 0xF;
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// don't erase the bootloader
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if (sec != 0 && sec < 12 && unlocked) {
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FLASH->CR = (sec << 3) | FLASH_CR_SER;
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FLASH->CR |= FLASH_CR_STRT;
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while (FLASH->SR & FLASH_SR_BSY);
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data_out[1] = 0xff;
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}
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break;
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case 0x12:
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if (data[2] <= 4 && unlocked) {
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set_led(LED_RED, 0);
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for (int i = 0; i < data[2]; i++) {
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// program byte 1
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FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;
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*prog_ptr = *(uint32_t*)(data+4+(i*4));
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while (FLASH->SR & FLASH_SR_BSY);
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// relock it
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FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
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//*(uint64_t*)(&spi_tx_buf[0x30+(i*4)]) = *prog_ptr;
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prog_ptr++;
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}
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set_led(LED_RED, 1);
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data_out[1] = 0xff;
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}
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break;
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case 0x13:
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// reset
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NVIC_SystemReset();
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break;
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default:
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break;
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}
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}
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return 8;
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}
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}*/
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void spi_flasher() {
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// green LED on for flashing
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GPIOC->MODER |= GPIO_MODER_MODER6_0;
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GPIOC->ODR &= ~(1 << 6);
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__disable_irq();
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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@ -32,112 +88,13 @@ void spi_flasher() {
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GPIOA->AFR[0] = GPIO_AF5_SPI1 << (4*4) | GPIO_AF5_SPI1 << (5*4) |
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GPIO_AF5_SPI1 << (6*4) | GPIO_AF5_SPI1 << (7*4);
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// blue LED on for flashing
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set_led(LED_BLUE, 1);
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// flasher
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spi_init();
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__enable_irq();
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unsigned char spi_rx_buf[0x14];
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unsigned char spi_tx_buf[0x44];
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int i;
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int sec;
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int rcv = 0;
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int lastval = (GPIOA->IDR & (1 << 4));
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uint32_t *prog_ptr = (uint32_t *)0x8004000;
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while (1) {
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int val = (GPIOA->IDR & (1 << 4));
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if (!val && lastval) {
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spi_rx_dma(spi_rx_buf, 0x14);
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rcv = 1;
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}
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lastval = val;
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if (rcv && (DMA2->LISR & DMA_LISR_TCIF2)) {
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DMA2->LIFCR = DMA_LIFCR_CTCIF2;
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rcv = 0;
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memset(spi_tx_buf, 0, 0x44);
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spi_tx_buf[0x40] = 0xde;
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spi_tx_buf[0x41] = 0xad;
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spi_tx_buf[0x42] = 0xd0;
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spi_tx_buf[0x43] = 0x0d;
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if (memcmp("\x00\x00\x00\x00\x40\xD0\x00\x00\x00\x00\x20\x00", spi_rx_buf, 0xC) == 0) {
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*(uint32_t*)(&spi_tx_buf[0]) = 0x20;
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memcpy(spi_tx_buf+4, (void *)0x1fff79e0, 0x20);
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} else if (spi_rx_buf[0] == (0xff^spi_rx_buf[1]) &&
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spi_rx_buf[2] == (0xff^spi_rx_buf[3])) {
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spi_tx_buf[0] = 0xff;
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*(uint32_t*)(&spi_tx_buf[4]) = FLASH->CR;
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*(uint32_t*)(&spi_tx_buf[8]) = (uint32_t)prog_ptr;
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// valid
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switch (spi_rx_buf[0]) {
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case 0x10:
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// unlock flash
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if (FLASH->CR & FLASH_CR_LOCK) {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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spi_tx_buf[1] = 0xff;
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}
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break;
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case 0x11:
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// erase
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sec = spi_rx_buf[2] & 0xF;
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// don't erase the bootloader
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if (sec != 0 && sec < 12) {
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FLASH->CR = (sec << 3) | FLASH_CR_SER;
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FLASH->CR |= FLASH_CR_STRT;
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while (FLASH->SR & FLASH_SR_BSY);
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spi_tx_buf[1] = 0xff;
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}
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break;
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case 0x12:
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if (spi_rx_buf[2] <= 4) {
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set_led(LED_RED, 0);
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for (i = 0; i < spi_rx_buf[2]; i++) {
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// program byte 1
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FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;
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*prog_ptr = *(uint32_t*)(spi_rx_buf+4+(i*4));
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while (FLASH->SR & FLASH_SR_BSY);
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*(uint64_t*)(&spi_tx_buf[0x30+(i*4)]) = *prog_ptr;
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prog_ptr++;
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}
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set_led(LED_RED, 1);
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spi_tx_buf[1] = 0xff;
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}
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break;
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case 0x13:
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// reset
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NVIC_SystemReset();
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break;
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case 0x14:
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// bootloader
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/*enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;
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NVIC_SystemReset();*/
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break;
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default:
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break;
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}
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memcpy(spi_tx_buf+0x10, spi_rx_buf, 0x14);
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while (1) { }
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}
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spi_tx_dma(spi_tx_buf, 0x44);
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// signal data is ready by driving low
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// esp must be configured as input by this point
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->MODER |= GPIO_MODER_MODER0_0;
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GPIOB->ODR &= ~(GPIO_ODR_ODR_0);
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}
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if (DMA2->LISR & DMA_LISR_TCIF3) {
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DMA2->LIFCR = DMA_LIFCR_CTCIF3;
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// reset handshake back to pull up
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GPIOB->MODER &= ~(GPIO_MODER_MODER0);
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GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0;
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}
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}
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}
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@ -56,7 +56,9 @@ static int ICACHE_FLASH_ATTR __spi_comm(char *dat, int len, uint32_t *recvData,
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SPIMasterSendData(SpiNum_HSPI, &spiData);
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// give the ST time to be ready, up to 1s
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for (int i = 0;(gpio_input_get() & (1 << 4)) && i < 100000; i++) os_delay_us(10);
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for (int i = 0;(gpio_input_get() & (1 << 4)) && i < 100000; i++) {
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os_delay_us(10);
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}
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// TODO: handle this better
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if (gpio_input_get() & (1 << 4)) os_printf("ERROR: SPI receive failed\n");
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@ -70,6 +72,10 @@ static int ICACHE_FLASH_ATTR __spi_comm(char *dat, int len, uint32_t *recvData,
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SPIMasterRecvData(SpiNum_HSPI, &spiData);
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int length = recvData[0];
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if (length > 0x40) {
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os_printf("SPI: BAD LENGTH RECEIVED\n");
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}
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// got response, 0x40 works, 0x44 does not
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spiData.data = recvData+1;
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spiData.dataLen = recvDataLen;
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@ -35,44 +35,61 @@ LOCAL os_timer_t ota_reboot_timer;
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#define FIRMWARE_SIZE 503808
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void st_flash() {
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void ICACHE_FLASH_ATTR st_flash() {
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int i;
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if (st_firmware != NULL) {
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// stupid watchdog test
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//system_soft_wdt_stop();
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// boot mode
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os_printf("st_flash: enter boot mode\n");
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st_set_boot_mode(1);
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// echo
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os_printf("st_flash: wait for echo\n");
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int i;
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for (i = 0; i < 10; i++) {
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if (st_cmd(0xf, 0, NULL) == 1) break;
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os_printf(" miss: %d\n", i);
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}
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// unlock flash
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os_printf("st_flash: unlock flash\n");
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st_cmd(0x10, 0, NULL);
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st_cmd(0xf, 0, NULL);
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// erase sector 1
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os_printf("st_flash: erase sector 1\n");
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st_cmd(0x11, 1, NULL);
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st_cmd(0xf, 0, NULL);
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if (real_content_length >= 16384) {
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// erase sector 2
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os_printf("st_flash: erase sector 2\n");
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st_cmd(0x11, 2, NULL);
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st_cmd(0xf, 0, NULL);
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}
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// real content length will always be 0x10 aligned
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os_printf("st_flash: flashing\n");
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for (i = 0; i < real_content_length; i += 0x10) {
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st_cmd(0x12, 4, &st_firmware[i]);
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if (!st_cmd(0x12, 4, &st_firmware[i])) {
|
||||
os_printf("st_flash: FAILED, BAILING\n");
|
||||
break;
|
||||
}
|
||||
system_soft_wdt_feed();
|
||||
}
|
||||
|
||||
// reboot into normal mode
|
||||
os_printf("st_flash: rebooting\n");
|
||||
st_set_boot_mode(0);
|
||||
|
||||
// done with this
|
||||
os_free(st_firmware);
|
||||
st_firmware = NULL;
|
||||
|
||||
// watchdog done
|
||||
//system_soft_wdt_restart();
|
||||
}
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
NOT_STARTED,
|
||||
|
|
@ -87,7 +104,7 @@ typedef enum {
|
|||
web_state_t state = NOT_STARTED;
|
||||
int esp_address, esp_address_erase_limit, start_address;
|
||||
|
||||
void hexdump(char *data, int len) {
|
||||
void ICACHE_FLASH_ATTR hexdump(char *data, int len) {
|
||||
int i;
|
||||
for (i=0;i<len;i++) {
|
||||
if (i!=0 && (i%0x10)==0) os_printf("\n");
|
||||
|
|
@ -96,7 +113,7 @@ void hexdump(char *data, int len) {
|
|||
os_printf("\n");
|
||||
}
|
||||
|
||||
void st_reset() {
|
||||
void ICACHE_FLASH_ATTR st_reset() {
|
||||
// reset the ST
|
||||
gpio16_output_conf();
|
||||
gpio16_output_set(0);
|
||||
|
|
@ -105,7 +122,7 @@ void st_reset() {
|
|||
os_delay_us(10000);
|
||||
}
|
||||
|
||||
void st_set_boot_mode(int boot_mode) {
|
||||
void ICACHE_FLASH_ATTR st_set_boot_mode(int boot_mode) {
|
||||
if (boot_mode) {
|
||||
// boot mode (pull low)
|
||||
gpio_output_set(0, (1 << 4), (1 << 4), 0);
|
||||
|
|
@ -115,9 +132,12 @@ void st_set_boot_mode(int boot_mode) {
|
|||
gpio_output_set((1 << 4), 0, (1 << 4), 0);
|
||||
st_reset();
|
||||
}
|
||||
|
||||
// float boot pin
|
||||
gpio_output_set(0, 0, 0, (1 << 4));
|
||||
}
|
||||
|
||||
int st_cmd(int d1, int d2, char *data) {
|
||||
int ICACHE_FLASH_ATTR st_cmd(int d1, int d2, char *data) {
|
||||
uint32_t __dat[0x14];
|
||||
char *dat = (char *)__dat;
|
||||
memset(dat, 0, 0x14);
|
||||
|
|
@ -127,10 +147,31 @@ int st_cmd(int d1, int d2, char *data) {
|
|||
dat[2] = d2;
|
||||
dat[3] = 0xFF^d2;
|
||||
if (data != NULL) memcpy(dat+4, data, 0x10);
|
||||
hexdump(dat, 0x14);
|
||||
//hexdump(dat, 0x14);
|
||||
|
||||
spi_comm(dat, 0x14, recv, 0x40);
|
||||
return memcmp(recv+0x10, "\xde\xad\xd0\x0d", 4)==0;
|
||||
//hexdump(recv, 0x44);
|
||||
int good = memcmp(recv+2, "\xde\xad\xd0\x0d", 4)==0;
|
||||
|
||||
if (!good) {
|
||||
os_printf("ST command failed!\n");
|
||||
hexdump(recv, 0x44);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (((uint8_t*)recv)[6] != d1) {
|
||||
os_printf("ST command WRONG\n");
|
||||
hexdump(recv, 0x44);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (((uint8_t*)recv)[5] != 0xFF) {
|
||||
os_printf("ST command logical fail\n");
|
||||
hexdump(recv, 0x44);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) {
|
||||
|
|
@ -182,7 +223,7 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) {
|
|||
// 0x1000 = user1.bin
|
||||
// 0x81000 = user2.bin
|
||||
// 0x3FE000 = blank.bin
|
||||
os_printf("init st firmware\n");
|
||||
os_printf("init esp firmware\n");
|
||||
char *cl = strstr(data, "Content-Length: ");
|
||||
if (cl != NULL) {
|
||||
// get content length
|
||||
|
|
|
|||
Loading…
Reference in New Issue