35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
void clock_init(void) {
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// enable external oscillator
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register_set_bits(&(RCC->CR), RCC_CR_HSEON);
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while ((RCC->CR & RCC_CR_HSERDY) == 0);
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// divide things
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// AHB = 96MHz
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// APB1 = 48MHz
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// APB2 = 48MHz
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register_set(&(RCC->CFGR), RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV2, 0xFF7FFCF3U);
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// 16MHz crystal
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// PLLM: 8
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// PLLN: 96
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// PLLP: 2
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// PLLQ: 4
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// P output: 96MHz
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// Q output: 48MHz
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register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_5 | RCC_PLLCFGR_PLLSRC_HSE, 0x7F437FFFU);
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// start PLL
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register_set_bits(&(RCC->CR), RCC_CR_PLLON);
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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// Configure Flash prefetch, Instruction cache, Data cache and wait state
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// *** without this, it breaks ***
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register_set(&(FLASH->ACR), FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS, 0x1F0FU);
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// switch to PLL
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register_set_bits(&(RCC->CFGR), RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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// *** running on PLL ***
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}
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