2022-03-15 08:32:20 +08:00
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// Define to prevent recursive inclusion
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#ifndef COMMS_H
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#define COMMS_H
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2022-03-16 03:29:05 +08:00
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#define OFFSET 0x8U
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#define BROADCAST_ADDR 0x7DFU
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#define FALLBACK_ADDR 0x7E0U
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#define FALLBACK_R_ADDR (FALLBACK_ADDR + OFFSET)
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2022-08-19 04:30:04 +08:00
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#define ENGINE_ADDR 0x720U
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#define ENGINE_R_ADDR (ENGINE_ADDR + OFFSET)
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#define DEBUG_ADDR 0x721U
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#define DEBUG_R_ADDR (DEBUG_ADDR + OFFSET)
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2022-03-16 03:29:05 +08:00
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2022-03-15 08:32:20 +08:00
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#include "drivers/llbxcan.h"
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2022-04-15 08:34:40 +08:00
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#include "uds.h"
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2022-03-15 08:32:20 +08:00
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2022-05-28 10:15:52 +08:00
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extern P rtP_Left;
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extern P rtP_Right;
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extern volatile int16_t cmdL; // global variable for Left Command
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extern volatile int16_t cmdR; // global variable for Right Command
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extern uint8_t hw_type;
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2022-06-24 05:34:01 +08:00
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extern board_t board;
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2022-03-15 08:32:20 +08:00
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extern uint32_t enter_bootloader_mode;
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2022-03-23 07:34:12 +08:00
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extern volatile uint32_t torque_cmd_timeout;
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2022-03-15 08:32:20 +08:00
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2022-09-07 04:08:46 +08:00
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extern volatile uint32_t ignition_off_counter;
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2022-04-05 08:17:10 +08:00
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const uint8_t crc_poly = 0xD5U; // standard crc8
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uint32_t current_idx = 0;
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2022-04-15 08:34:40 +08:00
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typedef struct {
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volatile uint32_t w_ptr;
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volatile uint32_t r_ptr;
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uint32_t fifo_size;
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CAN_FIFOMailBox_TypeDef *elems;
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} can_ring;
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#define can_buffer(x, size) \
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CAN_FIFOMailBox_TypeDef elems_##x[size]; \
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can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = (size), .elems = (CAN_FIFOMailBox_TypeDef *)&(elems_##x) };
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can_buffer(tx_q, 0x1A0)
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bool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
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bool ret = 0;
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if (q->w_ptr != q->r_ptr) {
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*elem = q->elems[q->r_ptr];
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if ((q->r_ptr + 1U) == q->fifo_size) {
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q->r_ptr = 0;
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} else {
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q->r_ptr += 1U;
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}
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ret = 1;
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}
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return ret;
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}
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bool can_push(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
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bool ret = false;
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uint32_t next_w_ptr;
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if ((q->w_ptr + 1U) == q->fifo_size) {
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next_w_ptr = 0;
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} else {
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next_w_ptr = q->w_ptr + 1U;
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}
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if (next_w_ptr != q->r_ptr) {
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q->elems[q->w_ptr] = *elem;
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q->w_ptr = next_w_ptr;
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ret = true;
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}
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return ret;
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}
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2022-03-16 03:29:05 +08:00
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void can_send_msg(uint32_t addr, uint32_t dhr, uint32_t dlr, uint8_t len) {
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2022-04-15 08:34:40 +08:00
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CAN_FIFOMailBox_TypeDef to_push;
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to_push.RDHR = dhr;
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to_push.RDLR = dlr;
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to_push.RDTR = len;
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to_push.RIR = ((addr >= 0x800U) ? ((addr << 3) | (1U << 2)) : (addr << 21)) | 1;
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2022-03-16 03:29:05 +08:00
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2022-04-15 08:34:40 +08:00
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can_push(&can_tx_q, &to_push);
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2022-03-16 03:29:05 +08:00
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}
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2022-04-15 08:34:40 +08:00
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void process_can(void) {
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2022-09-03 07:17:21 +08:00
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__disable_irq();
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2022-04-15 08:34:40 +08:00
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CAN_FIFOMailBox_TypeDef to_send;
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2022-09-03 05:04:33 +08:00
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if ((board.CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
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2022-04-15 08:34:40 +08:00
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if (can_pop(&can_tx_q, &to_send)) {
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2022-06-24 05:34:01 +08:00
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board.CAN->sTxMailBox[0].TDLR = to_send.RDLR;
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board.CAN->sTxMailBox[0].TDHR = to_send.RDHR;
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board.CAN->sTxMailBox[0].TDTR = to_send.RDTR;
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board.CAN->sTxMailBox[0].TIR = to_send.RIR;
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2022-04-05 13:17:35 +08:00
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}
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2022-03-16 03:29:05 +08:00
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}
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2022-09-03 07:17:21 +08:00
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__enable_irq();
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2022-03-16 03:29:05 +08:00
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}
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2022-06-24 05:34:01 +08:00
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void can_rx(void) {
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while ((board.CAN->RF0R & CAN_RF0R_FMP0) != 0) {
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2022-08-18 07:05:45 +08:00
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uint32_t address = board.CAN->sFIFOMailBox[0].RIR >> 21;
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if (address == (0x250U + board.can_addr_offset)) {
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2022-06-24 05:34:01 +08:00
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if ((GET_MAILBOX_BYTES_04(&board.CAN->sFIFOMailBox[0]) == 0xdeadface) && (GET_MAILBOX_BYTES_48(&board.CAN->sFIFOMailBox[0]) == 0x0ab00b1e)) {
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2022-03-16 03:29:05 +08:00
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enter_bootloader_mode = ENTER_SOFTLOADER_MAGIC;
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NVIC_SystemReset();
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2022-03-15 08:32:20 +08:00
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}
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2022-05-28 10:15:52 +08:00
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#define MSG_TRQ_LEN 6
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uint8_t dat[MSG_TRQ_LEN];
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for (int i=0; i<MSG_TRQ_LEN; i++) {
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2022-06-24 05:34:01 +08:00
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dat[i] = GET_MAILBOX_BYTE(&board.CAN->sFIFOMailBox[0], i);
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2022-03-15 08:32:20 +08:00
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}
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2022-04-05 08:17:10 +08:00
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uint16_t valueL = ((dat[0] << 8U) | dat[1]);
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uint16_t valueR = ((dat[2] << 8U) | dat[3]);
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uint8_t idx = dat[4] & 0xFU;
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if (crc_checksum(dat, 5, crc_poly) == dat[5]) {
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if (((current_idx + 1U) & 0xFU) == idx) {
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cmdL = valueL;
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cmdR = valueR;
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torque_cmd_timeout = 0;
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}
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current_idx = idx;
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}
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2022-07-25 22:00:16 +08:00
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out_enable(LED_BLUE, true);
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2022-08-18 07:05:45 +08:00
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} else if (address == (0x251U + board.can_addr_offset)) {
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2022-05-28 10:15:52 +08:00
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#define MSG_SPD_LEN 5
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uint8_t dat[MSG_TRQ_LEN];
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for (int i=0; i<MSG_TRQ_LEN; i++) {
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2022-06-24 05:34:01 +08:00
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dat[i] = GET_MAILBOX_BYTE(&board.CAN->sFIFOMailBox[0], i);
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2022-05-28 10:15:52 +08:00
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}
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uint16_t valueL = ((dat[0] << 8U) | dat[1]);
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uint16_t valueR = ((dat[2] << 8U) | dat[3]);
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if (crc_checksum(dat, 4, crc_poly) == dat[4]) {
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if ((valueL == 0) || (valueR == 0)) {
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rtP_Left.n_max = rtP_Right.n_max = N_MOT_MAX << 4;
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} else {
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rtP_Left.n_max = valueL << 4;
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rtP_Right.n_max = valueR << 4;
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}
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}
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2022-07-25 22:00:16 +08:00
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out_enable(LED_BLUE, true);
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2022-08-18 07:05:45 +08:00
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} else if ((address == BROADCAST_ADDR) || // Process UBS and OBD2 requests
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(address == FALLBACK_ADDR) ||
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2022-08-19 04:30:04 +08:00
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(address == (ENGINE_ADDR + board.uds_offset)) ||
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2022-08-18 07:05:45 +08:00
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(address == (DEBUG_ADDR + board.uds_offset))) {
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2022-06-24 05:34:01 +08:00
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process_uds(address, GET_MAILBOX_BYTES_04(&board.CAN->sFIFOMailBox[0]));
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2022-07-25 22:00:16 +08:00
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out_enable(LED_BLUE, true);
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2022-08-19 04:56:01 +08:00
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} else if ((hw_type == HW_TYPE_BASE) && (address == 0x203U + KNEE_ADDR_OFFSET)) { // detect knee by body and set flag for use with UDS message
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knee_detected = 1;
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2022-09-07 04:08:46 +08:00
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} else if ((hw_type == HW_TYPE_KNEE) && (address == 0x202U)) { // CAN based ignition for knee
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ignition_off_counter = 0;
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2022-03-16 03:29:05 +08:00
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}
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2022-03-15 08:32:20 +08:00
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// next
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2022-06-24 05:34:01 +08:00
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board.CAN->RF0R |= CAN_RF0R_RFOM0;
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2022-03-15 08:32:20 +08:00
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}
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}
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2022-06-24 05:34:01 +08:00
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void CAN1_TX_IRQHandler(void) {
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// clear interrupt
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board.CAN->TSR |= CAN_TSR_RQCP0;
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2022-09-07 04:17:53 +08:00
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process_can();
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2022-06-24 05:34:01 +08:00
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}
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void CAN1_SCE_IRQHandler(void) {
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llcan_clear_send(board.CAN);
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}
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void CAN1_RX0_IRQHandler(void) {
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can_rx();
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}
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void CAN2_TX_IRQHandler(void) {
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// clear interrupt
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board.CAN->TSR |= CAN_TSR_RQCP0;
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2022-09-07 04:17:53 +08:00
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process_can();
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2022-06-24 05:34:01 +08:00
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}
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void CAN2_SCE_IRQHandler(void) {
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llcan_clear_send(board.CAN);
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}
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void CAN2_RX0_IRQHandler(void) {
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can_rx();
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}
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2022-03-15 08:32:20 +08:00
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#endif
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