mirror of https://github.com/commaai/tinygrad.git
221 lines
8.7 KiB
Plaintext
221 lines
8.7 KiB
Plaintext
// ZinIrRegBitPrintOutDebug_7u_
|
|
|
|
Task_ID: 0
|
|
|
|
header = 10*4 = 0x28
|
|
|
|
aneTD.Header[0].TID = 0
|
|
aneTD.Header[0].NID = 0
|
|
aneTD.Header[0].LNID = 1
|
|
aneTD.Header[0].EON = 1
|
|
aneTD.Header[1].ExeCycles = 0
|
|
aneTD.Header[1].NextSize = 0
|
|
aneTD.Header[2].LogEvents = 1058
|
|
aneTD.Header[3].Exceptions = 0
|
|
aneTD.Header[4].DebugLogEvents = 16775274
|
|
aneTD.Header[5].DebugExceptions = 0
|
|
aneTD.Header[6].DisallowAbort = 0
|
|
aneTD.Header[6].TDSkip = 0
|
|
aneTD.Header[6].KPC = 0
|
|
aneTD.Header[6].SPL = 0
|
|
aneTD.Header[6].TSR = 0
|
|
aneTD.Header[6].SPC = 0
|
|
aneTD.Header[6].DPC = 0
|
|
aneTD.Header[6].TSE = 0
|
|
aneTD.Header[6].NextPriority = 0
|
|
aneTD.Header[6].TDE = 0
|
|
aneTD.Header[6].SrcLoc = 1
|
|
aneTD.Header[6].DstLoc = 1
|
|
aneTD.Header[6].TQDis = 0
|
|
aneTD.Header[7].NextPointer = 0
|
|
aneTD.Header[8].RBase0 = 5
|
|
aneTD.Header[8].RBE0 = 1
|
|
aneTD.Header[8].RBase1 = 0
|
|
aneTD.Header[8].RBE1 = 0
|
|
aneTD.Header[8].WBase = 4
|
|
aneTD.Header[8].WBE = 1
|
|
aneTD.Header[8].TBase = 0
|
|
aneTD.Header[8].TBE = 0
|
|
aneTD.Header[8].ENE = 1
|
|
aneTD.Header[9].KBase0 = 1
|
|
aneTD.Header[9].KBE0 = 1
|
|
aneTD.Header[9].KBase1 = 0
|
|
aneTD.Header[9].KBE1 = 0
|
|
aneTD.Header[9].KBase2 = 0
|
|
aneTD.Header[9].KBE2 = 0
|
|
aneTD.Header[9].KBase3 = 0
|
|
aneTD.Header[9].KBE3 = 0
|
|
|
|
0x28 = 00 F8 01 F4 = 0x1F800
|
|
+0x30
|
|
aneRegs.KernelDMASrc.CoeffBaseAddr[0].Addr = 0
|
|
aneRegs.KernelDMASrc.CoeffBfrSize[0].MemBfrSize = 2
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[0].CacheHint = 2
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[0].CrH = 0
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[0].En = 1
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[0].PrefetchParticipateEn = 0
|
|
aneRegs.KernelDMASrc.CoeffBaseAddr[1].Addr = 0
|
|
aneRegs.KernelDMASrc.CoeffBfrSize[1].MemBfrSize = 1
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[1].CacheHint = 2
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[1].CrH = 0
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[1].En = 0
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[1].PrefetchParticipateEn = 0
|
|
aneRegs.KernelDMASrc.CoeffBaseAddr[2].Addr = 0
|
|
aneRegs.KernelDMASrc.CoeffBfrSize[2].MemBfrSize = 1
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[2].CacheHint = 2
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[2].CrH = 0
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[2].En = 0
|
|
aneRegs.KernelDMASrc.CoeffDMAConfig[2].PrefetchParticipateEn = 0
|
|
# there's 13 more of these
|
|
aneRegs.KernelDMASrc.Spare0.Spare = 0
|
|
aneRegs.KernelDMASrc.Spare1.Spare = 0
|
|
|
|
0x124 = 00 00 00 3C = 0
|
|
+0x1d4
|
|
aneRegs.Common.Cfg.AccDoubleBufEn = 1
|
|
aneRegs.Common.Cfg.ActiveNE = 0
|
|
aneRegs.Common.Cfg.ContextSwitchIn = 0
|
|
aneRegs.Common.Cfg.ContextSwitchOut = 0
|
|
aneRegs.Common.Cfg.ShMax = 1
|
|
aneRegs.Common.Cfg.ShMin = 0
|
|
aneRegs.Common.Cfg.ShPref = 1
|
|
aneRegs.Common.Cfg.SmallSourceMode = 0
|
|
aneRegs.Common.ChCfg.InFmt = 2
|
|
aneRegs.Common.ChCfg.OutFmt = 2
|
|
aneRegs.Common.Cin.Cin = 1
|
|
aneRegs.Common.ConvCfg.Kh = 1
|
|
aneRegs.Common.ConvCfg.Kw = 1
|
|
aneRegs.Common.ConvCfg.OCGSize = 0
|
|
aneRegs.Common.ConvCfg.Ox = 1
|
|
aneRegs.Common.ConvCfg.Oy = 1
|
|
aneRegs.Common.ConvCfg.Px = 0
|
|
aneRegs.Common.ConvCfg.Py = 0
|
|
aneRegs.Common.ConvCfg.Sx = 1
|
|
aneRegs.Common.ConvCfg.Sy = 1
|
|
aneRegs.Common.Cout.Cout = 1
|
|
aneRegs.Common.DPE.Category = 0
|
|
aneRegs.Common.GroupConvCfg.ElemMultMode = 0
|
|
aneRegs.Common.GroupConvCfg.NumGroups = 1
|
|
aneRegs.Common.GroupConvCfg.UnicastCin = 1
|
|
aneRegs.Common.GroupConvCfg.UnicastEn = 1
|
|
aneRegs.Common.InDim.Hin = 1
|
|
aneRegs.Common.InDim.Win = 77
|
|
aneRegs.Common.OutDim.Hout = 1
|
|
aneRegs.Common.OutDim.Wout = 77
|
|
aneRegs.Common.Spare0.Spare = 0
|
|
aneRegs.Common.Spare1.Spare = 0
|
|
aneRegs.Common.TaskInfo.NID = 1
|
|
aneRegs.Common.TaskInfo.TaskID = 0
|
|
aneRegs.Common.TaskInfo.TaskQ = 0
|
|
aneRegs.Common.TileCfg.TileHeight = 1
|
|
|
|
0x168 = 00 38 01 6C = 0x13800
|
|
+0x220
|
|
aneRegs.TileDMASrc.BaseAddr.Addr = 0
|
|
aneRegs.TileDMASrc.DMAConfig.CacheHint = 2
|
|
aneRegs.TileDMASrc.DMAConfig.CacheHintNoReuse = 12
|
|
aneRegs.TileDMASrc.DMAConfig.CacheHintReuse = 14
|
|
aneRegs.TileDMASrc.DMAConfig.CrH = 0
|
|
aneRegs.TileDMASrc.DMAConfig.DependencyMode = 0
|
|
aneRegs.TileDMASrc.DMAConfig.En = 1
|
|
aneRegs.TileDMASrc.Fmt.CmpVec = 0
|
|
aneRegs.TileDMASrc.DepthStride.Stride = 3
|
|
aneRegs.TileDMASrc.Fmt.FmtMode = 1
|
|
aneRegs.TileDMASrc.Fmt.Interleave = 1
|
|
aneRegs.TileDMASrc.Fmt.MemFmt = 2
|
|
aneRegs.TileDMASrc.Fmt.OffsetCh = 0
|
|
aneRegs.TileDMASrc.Fmt.Shift = 0
|
|
aneRegs.TileDMASrc.Fmt.Truncate = 3
|
|
aneRegs.TileDMASrc.GroupStride.Stride = 0
|
|
aneRegs.TileDMASrc.PixelOffset[0].Offset = 0
|
|
aneRegs.TileDMASrc.PixelOffset[1].Offset = 0
|
|
aneRegs.TileDMASrc.PixelOffset[2].Offset = 0
|
|
aneRegs.TileDMASrc.PixelOffset[3].Offset = 0
|
|
aneRegs.TileDMASrc.PlaneStride.PlaneStride = 3
|
|
aneRegs.TileDMASrc.RowStride.Stride = 3
|
|
aneRegs.TileDMASrc.Spare0.Spare = 0
|
|
aneRegs.TileDMASrc.Spare1.Spare = 0
|
|
|
|
0x1dc = 00 48 00 44 = 0x4800
|
|
+0x29c
|
|
aneRegs.L2.ResultBase.Addr = 10
|
|
aneRegs.L2.ResultCfg.AliasConvRslt = 0
|
|
aneRegs.L2.ResultCfg.AliasConvSrc = 0
|
|
aneRegs.L2.ResultCfg.AliasPlanarRslt = 0
|
|
aneRegs.L2.ResultCfg.AliasPlanarSrc = 0
|
|
aneRegs.L2.ResultCfg.ResultType = 2
|
|
aneRegs.L2.ResultCfg.DMACmpVec = 0
|
|
aneRegs.L2.ResultCfg.DMAFmt = 1
|
|
aneRegs.L2.ResultCfg.DMAInterleave = 1
|
|
aneRegs.L2.ResultCfg.DMAOffsetCh = 0
|
|
aneRegs.L2.ResultCfg.L2BfrMode = 1
|
|
aneRegs.L2.ConvResultChannelStride.Stride = 0
|
|
aneRegs.L2.ConvResultRowStride.Stride = 0
|
|
aneRegs.L2.L2Cfg.InputReLU = 0
|
|
aneRegs.L2.L2Cfg.PaddingMode = 0
|
|
aneRegs.L2.Spare0.Spare = 0
|
|
aneRegs.L2.Spare1.Spare = 0
|
|
aneRegs.L2.SourceBase.Addr = 0
|
|
aneRegs.L2.SourceCfg.AliasConvRslt = 0
|
|
aneRegs.L2.SourceCfg.AliasConvSrc = 0
|
|
aneRegs.L2.SourceCfg.AliasPlanarRslt = 0
|
|
aneRegs.L2.SourceCfg.AliasPlanarSrc = 0
|
|
aneRegs.L2.SourceCfg.DMACmpVec = 0
|
|
aneRegs.L2.SourceCfg.DMAFmt = 1
|
|
aneRegs.L2.SourceCfg.DMAInterleave = 1
|
|
aneRegs.L2.SourceCfg.DMAOffsetCh = 0
|
|
aneRegs.L2.SourceCfg.Dependent = 0
|
|
aneRegs.L2.SourceCfg.SourceType = 2
|
|
aneRegs.L2.SourceChannelStride.Stride = 10
|
|
aneRegs.L2.SourceRowStride.Stride = 10
|
|
|
|
0x228 = 00 88 00 0C = 0x8800
|
|
+0x2f0
|
|
0x23C = 00 C8 00 10 = 0xC800
|
|
+0x30c
|
|
aneRegs.NE.AccBias.AccBias = 0
|
|
aneRegs.NE.AccBias.AccBiasShift = 0
|
|
aneRegs.NE.KernelCfg.GroupKernelReuse = 0
|
|
aneRegs.NE.KernelCfg.KernelFmt = 0
|
|
aneRegs.NE.KernelCfg.PalettizedBits = 8
|
|
aneRegs.NE.KernelCfg.PalettizedEn = 0
|
|
aneRegs.NE.KernelCfg.SparseFmt = 0
|
|
aneRegs.NE.MACCfg.BiasMode = 0
|
|
aneRegs.NE.MACCfg.BinaryPoint = 0
|
|
aneRegs.NE.MACCfg.KernelMode = 1
|
|
aneRegs.NE.MACCfg.MatrixBiasEn = 0
|
|
aneRegs.NE.MACCfg.NonlinearMode = 2
|
|
aneRegs.NE.MACCfg.OpMode = 4
|
|
aneRegs.NE.MACCfg.PostScaleMode = 0
|
|
aneRegs.NE.MatrixVectorBias.MatrixVectorBias = 0
|
|
aneRegs.NE.PostScale.PostRightShift = 0
|
|
aneRegs.NE.PostScale.PostScale = 15360
|
|
aneRegs.NE.Spare0.Spare = 0
|
|
aneRegs.NE.Spare1.Spare = 0
|
|
|
|
0x254 = 00 78 01 18 = 0x17800
|
|
+0x32c
|
|
aneRegs.TileDMADst.BaseAddr.Addr = 0
|
|
aneRegs.TileDMADst.DepthStride.DepthStride = 3
|
|
aneRegs.TileDMADst.DMAConfig.BypassEOW = 0
|
|
aneRegs.TileDMADst.DMAConfig.CacheHint = 3
|
|
aneRegs.TileDMADst.DMAConfig.CrH = 0
|
|
aneRegs.TileDMADst.DMAConfig.En = 1
|
|
aneRegs.TileDMADst.DMAConfig.L2BfrMode = 1
|
|
aneRegs.TileDMADst.Fmt.CmpVec = 0
|
|
aneRegs.TileDMADst.Fmt.CmpVecFill = 0
|
|
aneRegs.TileDMADst.Fmt.FmtMode = 1
|
|
aneRegs.TileDMADst.Fmt.Interleave = 1
|
|
aneRegs.TileDMADst.Fmt.MemFmt = 2
|
|
aneRegs.TileDMADst.Fmt.OffsetCh = 0
|
|
aneRegs.TileDMADst.Fmt.Shift = 0
|
|
aneRegs.TileDMADst.Fmt.Truncate = 3
|
|
aneRegs.TileDMADst.Fmt.ZeroPadFirst = 1
|
|
aneRegs.TileDMADst.Fmt.ZeroPadLast = 1
|
|
aneRegs.TileDMADst.GroupStride.GroupStride = 0
|
|
aneRegs.TileDMADst.PlaneStride.PlaneStride = 3
|
|
aneRegs.TileDMADst.RowStride.RowStride = 3
|
|
aneRegs.TileDMADst.Spare0.Spare = 0
|
|
aneRegs.TileDMADst.Spare1.Spare = 0
|
|
|