mirror of https://github.com/commaai/panda.git
268 lines
10 KiB
C
268 lines
10 KiB
C
// IRQs: FDCAN1_IT0, FDCAN1_IT1
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// FDCAN2_IT0, FDCAN2_IT1
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// FDCAN3_IT0, FDCAN3_IT1
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#define CANFD
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typedef struct {
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volatile uint32_t header[2];
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volatile uint32_t data_word[CANPACKET_DATA_SIZE_MAX/4U];
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} canfd_fifo;
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FDCAN_GlobalTypeDef *cans[] = {FDCAN1, FDCAN2, FDCAN3};
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uint8_t can_irq_number[3][2] = {
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{ FDCAN1_IT0_IRQn, FDCAN1_IT1_IRQn },
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{ FDCAN2_IT0_IRQn, FDCAN2_IT1_IRQn },
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{ FDCAN3_IT0_IRQn, FDCAN3_IT1_IRQn },
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};
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#define CAN_ACK_ERROR 3U
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bool can_set_speed(uint8_t can_number) {
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bool ret = true;
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FDCAN_GlobalTypeDef *FDCANx = CANIF_FROM_CAN_NUM(can_number);
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uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
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ret &= llcan_set_speed(
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FDCANx,
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bus_config[bus_number].can_speed,
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bus_config[bus_number].can_data_speed,
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bus_config[bus_number].canfd_non_iso,
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can_loopback,
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(unsigned int)(can_silent) & (1U << can_number)
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);
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return ret;
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}
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void update_can_health_pkt(uint8_t can_number, uint32_t ir_reg) {
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FDCAN_GlobalTypeDef *FDCANx = CANIF_FROM_CAN_NUM(can_number);
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uint32_t psr_reg = FDCANx->PSR;
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uint32_t ecr_reg = FDCANx->ECR;
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can_health[can_number].bus_off = ((psr_reg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
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can_health[can_number].bus_off_cnt += can_health[can_number].bus_off;
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can_health[can_number].error_warning = ((psr_reg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
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can_health[can_number].error_passive = ((psr_reg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
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can_health[can_number].last_error = ((psr_reg & FDCAN_PSR_LEC) >> FDCAN_PSR_LEC_Pos);
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if ((can_health[can_number].last_error != 0U) && (can_health[can_number].last_error != 7U)) {
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can_health[can_number].last_stored_error = can_health[can_number].last_error;
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}
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can_health[can_number].last_data_error = ((psr_reg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
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if ((can_health[can_number].last_data_error != 0U) && (can_health[can_number].last_data_error != 7U)) {
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can_health[can_number].last_data_stored_error = can_health[can_number].last_data_error;
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}
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can_health[can_number].receive_error_cnt = ((ecr_reg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
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can_health[can_number].transmit_error_cnt = ((ecr_reg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
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can_health[can_number].irq0_call_rate = interrupts[can_irq_number[can_number][0]].call_rate;
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can_health[can_number].irq1_call_rate = interrupts[can_irq_number[can_number][1]].call_rate;
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if (ir_reg != 0U) {
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// Clear error interrupts
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FDCANx->IR |= (FDCAN_IR_PED | FDCAN_IR_PEA | FDCAN_IR_EP | FDCAN_IR_BO | FDCAN_IR_RF0L);
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can_health[can_number].total_error_cnt += 1U;
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// Check for RX FIFO overflow
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if ((ir_reg & (FDCAN_IR_RF0L)) != 0U) {
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can_health[can_number].total_rx_lost_cnt += 1U;
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}
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// Cases:
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// 1. while multiplexing between buses 1 and 3 we are getting ACK errors that overwhelm CAN core, by resetting it recovers faster
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// 2. H7 gets stuck in bus off recovery state indefinitely
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if ((((can_health[can_number].last_error == CAN_ACK_ERROR) || (can_health[can_number].last_data_error == CAN_ACK_ERROR)) && (can_health[can_number].transmit_error_cnt > 127U)) ||
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((ir_reg & FDCAN_IR_BO) != 0U)) {
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can_health[can_number].can_core_reset_cnt += 1U;
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can_health[can_number].total_tx_lost_cnt += (FDCAN_TX_FIFO_EL_CNT - (FDCANx->TXFQS & FDCAN_TXFQS_TFFL)); // TX FIFO msgs will be lost after reset
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llcan_clear_send(FDCANx);
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}
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}
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}
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// ***************************** CAN *****************************
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// FDFDCANx_IT1 IRQ Handler (TX)
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void process_can(uint8_t can_number) {
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if (can_number != 0xffU) {
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ENTER_CRITICAL();
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FDCAN_GlobalTypeDef *FDCANx = CANIF_FROM_CAN_NUM(can_number);
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uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
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FDCANx->IR |= FDCAN_IR_TFE; // Clear Tx FIFO Empty flag
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if ((FDCANx->TXFQS & FDCAN_TXFQS_TFQF) == 0U) {
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CANPacket_t to_send;
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if (can_pop(can_queues[bus_number], &to_send)) {
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if (can_check_checksum(&to_send)) {
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can_health[can_number].total_tx_cnt += 1U;
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uint32_t TxFIFOSA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET) + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);
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// get the index of the next TX FIFO element (0 to FDCAN_TX_FIFO_EL_CNT - 1)
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uint32_t tx_index = (FDCANx->TXFQS >> FDCAN_TXFQS_TFQPI_Pos) & 0x1FU;
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// only send if we have received a packet
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canfd_fifo *fifo;
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fifo = (canfd_fifo *)(TxFIFOSA + (tx_index * FDCAN_TX_FIFO_EL_SIZE));
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fifo->header[0] = (to_send.extended << 30) | ((to_send.extended != 0U) ? (to_send.addr) : (to_send.addr << 18));
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uint32_t canfd_enabled_header = bus_config[can_number].canfd_enabled ? (1UL << 21) : 0UL;
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uint32_t brs_enabled_header = bus_config[can_number].brs_enabled ? (1UL << 20) : 0UL;
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fifo->header[1] = (to_send.data_len_code << 16) | canfd_enabled_header | brs_enabled_header;
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uint8_t data_len_w = (dlc_to_len[to_send.data_len_code] / 4U);
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data_len_w += ((dlc_to_len[to_send.data_len_code] % 4U) > 0U) ? 1U : 0U;
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for (unsigned int i = 0; i < data_len_w; i++) {
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BYTE_ARRAY_TO_WORD(fifo->data_word[i], &to_send.data[i*4U]);
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}
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FDCANx->TXBAR = (1UL << tx_index);
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// Send back to USB
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CANPacket_t to_push;
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to_push.returned = 1U;
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to_push.rejected = 0U;
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to_push.extended = to_send.extended;
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to_push.addr = to_send.addr;
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to_push.bus = bus_number;
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to_push.data_len_code = to_send.data_len_code;
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(void)memcpy(to_push.data, to_send.data, dlc_to_len[to_push.data_len_code]);
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can_set_checksum(&to_push);
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rx_buffer_overflow += can_push(&can_rx_q, &to_push) ? 0U : 1U;
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} else {
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can_health[can_number].total_tx_checksum_error_cnt += 1U;
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}
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refresh_can_tx_slots_available();
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}
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}
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EXIT_CRITICAL();
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}
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}
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// FDFDCANx_IT0 IRQ Handler (RX and errors)
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// blink blue when we are receiving CAN messages
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void can_rx(uint8_t can_number) {
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FDCAN_GlobalTypeDef *FDCANx = CANIF_FROM_CAN_NUM(can_number);
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uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
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uint32_t ir_reg = FDCANx->IR;
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// Clear all new messages from Rx FIFO 0
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FDCANx->IR |= FDCAN_IR_RF0N;
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while((FDCANx->RXF0S & FDCAN_RXF0S_F0FL) != 0U) {
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can_health[can_number].total_rx_cnt += 1U;
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// can is live
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pending_can_live = 1;
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// get the index of the next RX FIFO element (0 to FDCAN_RX_FIFO_0_EL_CNT - 1)
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uint32_t rx_fifo_idx = (uint8_t)((FDCANx->RXF0S >> FDCAN_RXF0S_F0GI_Pos) & 0x3FU);
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// Recommended to offset get index by at least +1 if RX FIFO is in overwrite mode and full (datasheet)
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if((FDCANx->RXF0S & FDCAN_RXF0S_F0F) == FDCAN_RXF0S_F0F) {
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rx_fifo_idx = ((rx_fifo_idx + 1U) >= FDCAN_RX_FIFO_0_EL_CNT) ? 0U : (rx_fifo_idx + 1U);
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can_health[can_number].total_rx_lost_cnt += 1U; // At least one message was lost
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}
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uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);
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CANPacket_t to_push;
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canfd_fifo *fifo;
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// getting address
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fifo = (canfd_fifo *)(RxFIFO0SA + (rx_fifo_idx * FDCAN_RX_FIFO_0_EL_SIZE));
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to_push.returned = 0U;
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to_push.rejected = 0U;
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to_push.extended = (fifo->header[0] >> 30) & 0x1U;
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to_push.addr = ((to_push.extended != 0U) ? (fifo->header[0] & 0x1FFFFFFFU) : ((fifo->header[0] >> 18) & 0x7FFU));
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to_push.bus = bus_number;
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to_push.data_len_code = ((fifo->header[1] >> 16) & 0xFU);
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bool canfd_frame = ((fifo->header[1] >> 21) & 0x1U);
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bool brs_frame = ((fifo->header[1] >> 20) & 0x1U);
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uint8_t data_len_w = (dlc_to_len[to_push.data_len_code] / 4U);
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data_len_w += ((dlc_to_len[to_push.data_len_code] % 4U) > 0U) ? 1U : 0U;
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for (unsigned int i = 0; i < data_len_w; i++) {
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WORD_TO_BYTE_ARRAY(&to_push.data[i*4U], fifo->data_word[i]);
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}
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can_set_checksum(&to_push);
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// forwarding (panda only)
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int bus_fwd_num = safety_fwd_hook(bus_number, to_push.addr);
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if (bus_fwd_num < 0) {
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bus_fwd_num = bus_config[can_number].forwarding_bus;
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}
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if (bus_fwd_num != -1) {
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CANPacket_t to_send;
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to_send.returned = 0U;
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to_send.rejected = 0U;
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to_send.extended = to_push.extended;
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to_send.addr = to_push.addr;
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to_send.bus = to_push.bus;
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to_send.data_len_code = to_push.data_len_code;
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(void)memcpy(to_send.data, to_push.data, dlc_to_len[to_push.data_len_code]);
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can_set_checksum(&to_send);
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can_send(&to_send, bus_fwd_num, true);
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can_health[can_number].total_fwd_cnt += 1U;
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}
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safety_rx_invalid += safety_rx_hook(&to_push) ? 0U : 1U;
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ignition_can_hook(&to_push);
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current_board->set_led(LED_BLUE, true);
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rx_buffer_overflow += can_push(&can_rx_q, &to_push) ? 0U : 1U;
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// Enable CAN FD and BRS if CAN FD message was received
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if (!(bus_config[can_number].canfd_enabled) && (canfd_frame)) {
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bus_config[can_number].canfd_enabled = true;
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}
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if (!(bus_config[can_number].brs_enabled) && (brs_frame)) {
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bus_config[can_number].brs_enabled = true;
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}
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// update read index
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FDCANx->RXF0A = rx_fifo_idx;
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}
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// Error handling
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if ((ir_reg & (FDCAN_IR_PED | FDCAN_IR_PEA | FDCAN_IR_EP | FDCAN_IR_BO | FDCAN_IR_RF0L)) != 0U) {
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update_can_health_pkt(can_number, ir_reg);
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}
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}
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void FDCAN1_IT0_IRQ_Handler(void) { can_rx(0); }
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void FDCAN1_IT1_IRQ_Handler(void) { process_can(0); }
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void FDCAN2_IT0_IRQ_Handler(void) { can_rx(1); }
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void FDCAN2_IT1_IRQ_Handler(void) { process_can(1); }
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void FDCAN3_IT0_IRQ_Handler(void) { can_rx(2); }
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void FDCAN3_IT1_IRQ_Handler(void) { process_can(2); }
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bool can_init(uint8_t can_number) {
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bool ret = false;
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REGISTER_INTERRUPT(FDCAN1_IT0_IRQn, FDCAN1_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)
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REGISTER_INTERRUPT(FDCAN1_IT1_IRQn, FDCAN1_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)
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REGISTER_INTERRUPT(FDCAN2_IT0_IRQn, FDCAN2_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)
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REGISTER_INTERRUPT(FDCAN2_IT1_IRQn, FDCAN2_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)
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REGISTER_INTERRUPT(FDCAN3_IT0_IRQn, FDCAN3_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)
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REGISTER_INTERRUPT(FDCAN3_IT1_IRQn, FDCAN3_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)
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if (can_number != 0xffU) {
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FDCAN_GlobalTypeDef *FDCANx = CANIF_FROM_CAN_NUM(can_number);
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ret &= can_set_speed(can_number);
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ret &= llcan_init(FDCANx);
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// in case there are queued up messages
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process_can(can_number);
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}
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return ret;
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}
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