mirror of https://github.com/commaai/panda.git
91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
void llspi_miso_dma(uint8_t *addr, int len) {
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// disable DMA
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DMA2_Stream3->CR &= ~DMA_SxCR_EN;
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register_clear_bits(&(SPI1->CR2), SPI_CR2_TXDMAEN);
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// setup source and length
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register_set(&(DMA2_Stream3->M0AR), (uint32_t)addr, 0xFFFFFFFFU);
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DMA2_Stream3->NDTR = len;
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// enable DMA
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register_set_bits(&(SPI1->CR2), SPI_CR2_TXDMAEN);
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DMA2_Stream3->CR |= DMA_SxCR_EN;
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}
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void llspi_mosi_dma(uint8_t *addr, int len) {
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// disable DMA
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register_clear_bits(&(SPI1->CR2), SPI_CR2_RXDMAEN);
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DMA2_Stream2->CR &= ~DMA_SxCR_EN;
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// drain the bus
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volatile uint8_t dat = SPI1->DR;
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(void)dat;
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// setup destination and length
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register_set(&(DMA2_Stream2->M0AR), (uint32_t)addr, 0xFFFFFFFFU);
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DMA2_Stream2->NDTR = len;
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// enable DMA
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DMA2_Stream2->CR |= DMA_SxCR_EN;
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register_set_bits(&(SPI1->CR2), SPI_CR2_RXDMAEN);
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}
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// SPI MOSI DMA FINISHED
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void DMA2_Stream2_IRQ_Handler(void) {
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// Clear interrupt flag
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ENTER_CRITICAL();
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DMA2->LIFCR = DMA_LIFCR_CTCIF2;
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spi_rx_done();
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EXIT_CRITICAL();
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}
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// SPI MISO DMA FINISHED
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void DMA2_Stream3_IRQ_Handler(void) {
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// Clear interrupt flag
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DMA2->LIFCR = DMA_LIFCR_CTCIF3;
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// Wait until the transaction is actually finished and clear the DR
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// Timeout to prevent hang when the master clock stops.
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bool timed_out = false;
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uint32_t start_time = microsecond_timer_get();
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while (!(SPI1->SR & SPI_SR_TXE)) {
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if (get_ts_elapsed(microsecond_timer_get(), start_time) > SPI_TIMEOUT_US) {
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timed_out = true;
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break;
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}
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}
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volatile uint8_t dat = SPI1->DR;
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(void)dat;
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SPI1->DR = 0U;
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if (timed_out) {
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print("SPI: TX timeout\n");
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}
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spi_tx_done(timed_out);
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}
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// ***************************** SPI init *****************************
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void llspi_init(void) {
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REGISTER_INTERRUPT(DMA2_Stream2_IRQn, DMA2_Stream2_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
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REGISTER_INTERRUPT(DMA2_Stream3_IRQn, DMA2_Stream3_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
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// Setup MOSI DMA
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register_set(&(DMA2_Stream2->CR), (DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_TCIE), 0x1E077EFEU);
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register_set(&(DMA2_Stream2->PAR), (uint32_t)&(SPI1->DR), 0xFFFFFFFFU);
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// Setup MISO DMA
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register_set(&(DMA2_Stream3->CR), (DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_TCIE), 0x1E077EFEU);
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register_set(&(DMA2_Stream3->PAR), (uint32_t)&(SPI1->DR), 0xFFFFFFFFU);
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// Enable SPI and the error interrupts
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// TODO: verify clock phase and polarity
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register_set(&(SPI1->CR1), SPI_CR1_SPE, 0xFFFFU);
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register_set(&(SPI1->CR2), 0U, 0xF7U);
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NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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}
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