From 0a32b17513fde6ad51c2410ee72ce727ce5847ea Mon Sep 17 00:00:00 2001
From: Igor Biletskyy <briskspirit@users.noreply.github.com>
Date: Thu, 24 Aug 2023 16:56:31 -0700
Subject: [PATCH] H7: few more Kb of RAM found (#1605)

* init

* remove discard
---
 board/drivers/can_common.h       |  6 ++---
 board/drivers/spi.h              |  4 +--
 board/stm32h7/stm32h7x5_flash.ld | 45 ++++++++++++++++++++++++--------
 tests/check_fw_size.py           | 20 ++++++++------
 4 files changed, 51 insertions(+), 24 deletions(-)

diff --git a/board/drivers/can_common.h b/board/drivers/can_common.h
index 4ad5b767f..985bfa0f5 100644
--- a/board/drivers/can_common.h
+++ b/board/drivers/can_common.h
@@ -53,9 +53,9 @@ void process_can(uint8_t can_number);
   can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = (size), .elems = (CANPacket_t *)&(elems_##x) };
 
 #ifdef STM32H7
-__attribute__((section(".ram_d1"))) can_buffer(rx_q, 0x1000)
-__attribute__((section(".ram_d1"))) can_buffer(tx2_q, 0x1A0)
-__attribute__((section(".ram_d2"))) can_buffer(txgmlan_q, 0x1A0)
+__attribute__((section(".axisram"))) can_buffer(rx_q, 0x1000)
+__attribute__((section(".axisram"))) can_buffer(tx2_q, 0x1A0)
+__attribute__((section(".sram12"))) can_buffer(txgmlan_q, 0x1A0)
 #else
 can_buffer(rx_q, 0x1000)
 can_buffer(tx2_q, 0x1A0)
diff --git a/board/drivers/spi.h b/board/drivers/spi.h
index af9dd8a57..25a70965d 100644
--- a/board/drivers/spi.h
+++ b/board/drivers/spi.h
@@ -10,8 +10,8 @@
 
 #ifdef STM32H7
 #define SPI_BUF_SIZE 2048U
-__attribute__((section(".ram_d1"))) uint8_t spi_buf_rx[SPI_BUF_SIZE];
-__attribute__((section(".ram_d2"))) uint8_t spi_buf_tx[SPI_BUF_SIZE];
+__attribute__((section(".axisram"))) uint8_t spi_buf_rx[SPI_BUF_SIZE];
+__attribute__((section(".sram12"))) uint8_t spi_buf_tx[SPI_BUF_SIZE];
 #else
 #define SPI_BUF_SIZE 1024U
 uint8_t spi_buf_rx[SPI_BUF_SIZE];
diff --git a/board/stm32h7/stm32h7x5_flash.ld b/board/stm32h7/stm32h7x5_flash.ld
index 5aef66374..3b6eee5dd 100644
--- a/board/stm32h7/stm32h7x5_flash.ld
+++ b/board/stm32h7/stm32h7x5_flash.ld
@@ -64,12 +64,17 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Specify the memory areas */
 MEMORY
 {
+/* RAM */
+BACKUP_SRAM (xrw)  : ORIGIN = 0x38800000, LENGTH = 4K /* Backup SRAM(4kb) */
+SRAM4 (xrw)        : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4(16kb) best for BDMA and SDMMC1*/
+SRAM12 (xrw)       : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1(16kb) + SRAM2(16kb), not for BDMA or SDMMC1 */
+AXISRAM (xrw)      : ORIGIN = 0x24000000, LENGTH = 320K /* AXI SRAM */
 DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K /* DTCM */
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 320K /* AXI SRAM */
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1(16kb) + SRAM2(16kb) */
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 */
+
+/* Code */
+SYSTEM (rx)        : ORIGIN = 0x1FF00000, LENGTH = 128K /* System memory */
+FLASH (rx)         : ORIGIN = 0x08000000, LENGTH = 1024K
 ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
 }
 
 /* Define output sections */
@@ -141,7 +146,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -180,17 +185,35 @@ SECTIONS
     . = ALIGN(8);
   } >DTCMRAM
 
-  .ram_d1 (NOLOAD) :
+  .itcmram (NOLOAD) :
   {
     . = ALIGN(4);
-    *(.ram_d1*)
-  } >RAM_D1
+    *(.itcmram*)
+  } >ITCMRAM
 
-  .ram_d2 (NOLOAD) :
+  .axisram (NOLOAD) :
   {
     . = ALIGN(4);
-    *(.ram_d2*)
-  } >RAM_D2
+    *(.axisram*)
+  } >AXISRAM
+
+  .sram12 (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.sram12*)
+  } >SRAM12
+
+  .sram4 (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.sram4*)
+  } >SRAM4
+
+  .backup_sram (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.backup_sram*)
+  } >BACKUP_SRAM
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
diff --git a/tests/check_fw_size.py b/tests/check_fw_size.py
index 4c2cb3d44..53681c5a3 100755
--- a/tests/check_fw_size.py
+++ b/tests/check_fw_size.py
@@ -7,15 +7,16 @@ def check_space(file, mcu):
   MCUS = {
     "H7": {
       ".flash": 1024*1024, # FLASH
-      ".ram_dtcm": 128*1024, # DTCMRAM
-      ".ram_d1": 320*1024, # AXI SRAM
-      ".ram_d2": 32*1024, # SRAM1(16kb) + SRAM2(16kb)
-      ".ram_d3": 16*1024, # SRAM4
-      ".ram_itcm": 64*1024, # ITCMRAM
+      ".dtcmram": 128*1024, # DTCMRAM
+      ".itcmram": 64*1024, # ITCMRAM
+      ".axisram": 320*1024, # AXI SRAM
+      ".sram12": 32*1024, # SRAM1(16kb) + SRAM2(16kb)
+      ".sram4": 16*1024, # SRAM4
+      ".backup_sram": 4*1024, # SRAM4
     },
     "F4": {
       ".flash": 1024*1024, # FLASH
-      ".ram_dtcm": 256*1024, # RAM
+      ".dtcmram": 256*1024, # RAM
       ".ram_d1": 64*1024, # RAM2
     },
   }
@@ -29,7 +30,10 @@ def check_space(file, mcu):
     ".debug_str",
     ".debug_ranges",
     ".debug_loc",
-    ".debug_frame"
+    ".debug_frame",
+    ".debug_line_str",
+    ".debug_rnglists",
+    ".debug_loclists",
   ]
   FLASH = [
     ".isr_vector",
@@ -59,7 +63,7 @@ def check_space(file, mcu):
         calcs[".flash"] += int(line[1], 16)
         pop = True
       if line[0] in RAM:
-        calcs[".ram_dtcm"] += int(line[1], 16)
+        calcs[".dtcmram"] += int(line[1], 16)
         pop = True
       if pop:
         result.pop(line[0])