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https://github.com/infiniteCable2/panda.git
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5ac6305a95
* remove DPANDA * -22 * lil more * canfd * lil more * update cppcheck * uart cleanup * always harness * sbu sense * lil more * enable spi * rm ENABLE_SPI
32 lines
1.3 KiB
C
32 lines
1.3 KiB
C
// ***************************** Interrupt handlers *****************************
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void uart_tx_ring(uart_ring *q){
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ENTER_CRITICAL();
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// Send out next byte of TX buffer
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if (q->w_ptr_tx != q->r_ptr_tx) {
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// Only send if transmit register is empty (aka last byte has been sent)
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if ((q->uart->SR & USART_SR_TXE) != 0U) {
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q->uart->DR = q->elems_tx[q->r_ptr_tx]; // This clears TXE
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q->r_ptr_tx = (q->r_ptr_tx + 1U) % q->tx_fifo_size;
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}
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// Enable TXE interrupt if there is still data to be sent
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if(q->r_ptr_tx != q->w_ptr_tx){
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q->uart->CR1 |= USART_CR1_TXEIE;
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} else {
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q->uart->CR1 &= ~USART_CR1_TXEIE;
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}
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}
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EXIT_CRITICAL();
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}
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// This read after reading SR clears all error interrupts. We don't want compiler warnings, nor optimizations
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#define UART_READ_DR(uart) volatile uint8_t t = (uart)->DR; UNUSED(t);
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// ***************************** Hardware setup *****************************
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#define DIV_(_PCLK_, _BAUD_) (((_PCLK_) * 25U) / (4U * (_BAUD_)))
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#define DIVMANT_(_PCLK_, _BAUD_) (DIV_((_PCLK_), (_BAUD_)) / 100U)
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#define DIVFRAQ_(_PCLK_, _BAUD_) ((((DIV_((_PCLK_), (_BAUD_)) - (DIVMANT_((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
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#define USART_BRR_(_PCLK_, _BAUD_) ((DIVMANT_((_PCLK_), (_BAUD_)) << 4) | (DIVFRAQ_((_PCLK_), (_BAUD_)) & 0x0FU))
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