From d41a0abef6db6d3f2db6efd9b04570a284aeff29 Mon Sep 17 00:00:00 2001 From: Igor Biletksyy Date: Tue, 29 Aug 2023 16:10:50 -0700 Subject: [PATCH] H7: comments for RAM organization reasoning --- board/drivers/can_common.h | 1 + board/drivers/spi.h | 1 + 2 files changed, 2 insertions(+) diff --git a/board/drivers/can_common.h b/board/drivers/can_common.h index 088319cb..f8bff5c2 100644 --- a/board/drivers/can_common.h +++ b/board/drivers/can_common.h @@ -57,6 +57,7 @@ void process_can(uint8_t can_number); #define GMLAN_TX_BUFFER_SIZE 416U #ifdef STM32H7 +// ITCM RAM and DTCM RAM are the fastest for Cortex-M7 core access __attribute__((section(".axisram"))) can_buffer(rx_q, CAN_RX_BUFFER_SIZE) __attribute__((section(".itcmram"))) can_buffer(tx1_q, CAN_TX_BUFFER_SIZE) __attribute__((section(".itcmram"))) can_buffer(tx2_q, CAN_TX_BUFFER_SIZE) diff --git a/board/drivers/spi.h b/board/drivers/spi.h index c91b5f4d..6d0beda9 100644 --- a/board/drivers/spi.h +++ b/board/drivers/spi.h @@ -10,6 +10,7 @@ #ifdef STM32H7 #define SPI_BUF_SIZE 2048U +// H7 DMA2 located in D2 domain, so we need to use SRAM1/SRAM2 __attribute__((section(".sram12"))) uint8_t spi_buf_rx[SPI_BUF_SIZE]; __attribute__((section(".sram12"))) uint8_t spi_buf_tx[SPI_BUF_SIZE]; #else