From ad4f69cd18954e06789c5e404175ff1cf8db7ea0 Mon Sep 17 00:00:00 2001
From: Robbe Derks <robbe.derks@gmail.com>
Date: Thu, 7 Apr 2022 02:19:42 +0200
Subject: [PATCH] Dos: PWM based camera signals (#912)

* switch over to PWM based camera signals

* update comment

Co-authored-by: Comma Device <device@comma.ai>
Co-authored-by: Willem Melching <willem.melching@gmail.com>
---
 board/boards/dos.h           |  4 ++--
 board/stm32fx/clock_source.h | 32 ++++++++++++++++++++++++++++----
 2 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/board/boards/dos.h b/board/boards/dos.h
index 46354a54..e1252eca 100644
--- a/board/boards/dos.h
+++ b/board/boards/dos.h
@@ -183,8 +183,8 @@ void dos_init(void) {
     can_flip_buses(0, 2);
   }
 
-  // Init clock source as internal free running
-  dos_set_clock_source_mode(CLOCK_SOURCE_MODE_FREE_RUNNING);
+  // Init clock source (camera strobe) using PWM
+  dos_set_clock_source_mode(CLOCK_SOURCE_MODE_PWM);
 }
 
 const harness_configuration dos_harness_config = {
diff --git a/board/stm32fx/clock_source.h b/board/stm32fx/clock_source.h
index 26c1cfa8..f8fea5fc 100644
--- a/board/stm32fx/clock_source.h
+++ b/board/stm32fx/clock_source.h
@@ -1,6 +1,7 @@
 
 #define CLOCK_SOURCE_MODE_DISABLED       0U
 #define CLOCK_SOURCE_MODE_FREE_RUNNING   1U
+#define CLOCK_SOURCE_MODE_PWM            2U
 
 #define CLOCK_SOURCE_PERIOD_MS           50U
 #define CLOCK_SOURCE_PULSE_LEN_MS        2U
@@ -9,7 +10,7 @@ uint8_t clock_source_mode = CLOCK_SOURCE_MODE_DISABLED;
 
 void TIM1_UP_TIM10_IRQ_Handler(void) {
   if((TIM1->SR & TIM_SR_UIF) != 0) {
-    if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {
+    if(clock_source_mode == CLOCK_SOURCE_MODE_FREE_RUNNING) {
       // Start clock pulse
       set_gpio_output(GPIOB, 14, true);
       set_gpio_output(GPIOB, 15, true);
@@ -23,7 +24,7 @@ void TIM1_UP_TIM10_IRQ_Handler(void) {
 
 void TIM1_CC_IRQ_Handler(void) {
   if((TIM1->SR & TIM_SR_CC1IF) != 0) {
-    if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {
+    if(clock_source_mode == CLOCK_SOURCE_MODE_FREE_RUNNING) {
       // End clock pulse
       set_gpio_output(GPIOB, 14, false);
       set_gpio_output(GPIOB, 15, false);
@@ -39,11 +40,13 @@ void clock_source_init(uint8_t mode){
   // Setup timer
   REGISTER_INTERRUPT(TIM1_UP_TIM10_IRQn, TIM1_UP_TIM10_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)
   REGISTER_INTERRUPT(TIM1_CC_IRQn, TIM1_CC_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)
-  register_set(&(TIM1->PSC), ((APB2_FREQ*100U)-1U), 0xFFFFU);                   // Tick on 0.1 ms
+  register_set(&(TIM1->PSC), ((APB2_FREQ*100U)-1U), 0xFFFFU);                 // Tick on 0.1 ms
   register_set(&(TIM1->ARR), ((CLOCK_SOURCE_PERIOD_MS*10U) - 1U), 0xFFFFU);   // Period
   register_set(&(TIM1->CCMR1), 0U, 0xFFFFU);                                  // No output on compare
-  register_set_bits(&(TIM1->CCER), TIM_CCER_CC1E);                            // Enable compare 1
+  register_set(&(TIM1->CCER), TIM_CCER_CC1E, 0xFFFFU);                        // Enable compare 1
   register_set(&(TIM1->CCR1), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU);      // Compare 1 value
+  register_set(&(TIM1->CCR2), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU);      // Compare 1 value
+  register_set(&(TIM1->CCR3), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU);      // Compare 1 value
   register_set_bits(&(TIM1->DIER), TIM_DIER_UIE | TIM_DIER_CC1IE);            // Enable interrupts
   register_set(&(TIM1->CR1), TIM_CR1_CEN, 0x3FU);                             // Enable timer
 
@@ -67,6 +70,27 @@ void clock_source_init(uint8_t mode){
 
       clock_source_mode = CLOCK_SOURCE_MODE_FREE_RUNNING;
       break;
+    case CLOCK_SOURCE_MODE_PWM:
+      // No interrupts
+      NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
+      NVIC_DisableIRQ(TIM1_CC_IRQn);
+
+      // Set GPIO as timer channels
+      set_gpio_alternate(GPIOB, 14, GPIO_AF1_TIM1);
+      set_gpio_alternate(GPIOB, 15, GPIO_AF1_TIM1);
+
+      // Set PWM mode
+      register_set(&(TIM1->CCMR1), (0b110 << TIM_CCMR1_OC2M_Pos), 0xFFFFU);
+      register_set(&(TIM1->CCMR2), (0b110 << TIM_CCMR2_OC3M_Pos), 0xFFFFU);
+
+      // Enable output
+      register_set(&(TIM1->BDTR), TIM_BDTR_MOE, 0xFFFFU);
+
+      // Enable complementary compares
+      register_set_bits(&(TIM1->CCER), TIM_CCER_CC2NE | TIM_CCER_CC3NE);
+
+      clock_source_mode = CLOCK_SOURCE_MODE_PWM;
+      break;
     default:
       puts("Unknown clock source mode: "); puth(mode); puts("\n");
       break;