mirror of
https://github.com/dragonpilot/dragonpilot.git
synced 2026-02-25 16:23:56 +08:00
100 lines
3.4 KiB
C
100 lines
3.4 KiB
C
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#define CLOCK_SOURCE_MODE_DISABLED 0U
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#define CLOCK_SOURCE_MODE_FREE_RUNNING 1U
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#define CLOCK_SOURCE_MODE_EXTERNAL_SYNC 2U
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#define CLOCK_SOURCE_PERIOD_MS 50U
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#define CLOCK_SOURCE_PULSE_LEN_MS 2U
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uint8_t clock_source_mode = CLOCK_SOURCE_MODE_DISABLED;
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void EXTI0_IRQ_Handler(void) {
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volatile unsigned int pr = EXTI->PR & (1U << 0);
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if (pr != 0U) {
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if(clock_source_mode == CLOCK_SOURCE_MODE_EXTERNAL_SYNC){
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// TODO: Implement!
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}
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}
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EXTI->PR = (1U << 0);
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}
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void TIM1_UP_TIM10_IRQ_Handler(void) {
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if((TIM1->SR & TIM_SR_UIF) != 0) {
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if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {
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// Start clock pulse
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set_gpio_output(GPIOB, 14, true);
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set_gpio_output(GPIOB, 15, true);
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}
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// Reset interrupt
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TIM1->SR &= ~(TIM_SR_UIF);
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}
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}
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void TIM1_CC_IRQ_Handler(void) {
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if((TIM1->SR & TIM_SR_CC1IF) != 0) {
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if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {
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// End clock pulse
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set_gpio_output(GPIOB, 14, false);
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set_gpio_output(GPIOB, 15, false);
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}
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// Reset interrupt
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TIM1->SR &= ~(TIM_SR_CC1IF);
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}
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}
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void clock_source_init(uint8_t mode){
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// Setup external clock signal interrupt
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REGISTER_INTERRUPT(EXTI0_IRQn, EXTI0_IRQ_Handler, 110U, FAULT_INTERRUPT_RATE_CLOCK_SOURCE)
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register_set(&(SYSCFG->EXTICR[0]), SYSCFG_EXTICR1_EXTI0_PB, 0xFU);
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register_set_bits(&(EXTI->IMR), (1U << 0));
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register_set_bits(&(EXTI->RTSR), (1U << 0));
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register_clear_bits(&(EXTI->FTSR), (1U << 0));
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// Setup timer
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REGISTER_INTERRUPT(TIM1_UP_TIM10_IRQn, TIM1_UP_TIM10_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)
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REGISTER_INTERRUPT(TIM1_CC_IRQn, TIM1_CC_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)
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register_set(&(TIM1->PSC), (9600-1), 0xFFFFU); // Tick on 0.1 ms
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register_set(&(TIM1->ARR), ((CLOCK_SOURCE_PERIOD_MS*10U) - 1U), 0xFFFFU); // Period
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register_set(&(TIM1->CCMR1), 0U, 0xFFFFU); // No output on compare
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register_set_bits(&(TIM1->CCER), TIM_CCER_CC1E); // Enable compare 1
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register_set(&(TIM1->CCR1), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 1 value
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register_set_bits(&(TIM1->DIER), TIM_DIER_UIE | TIM_DIER_CC1IE); // Enable interrupts
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register_set(&(TIM1->CR1), TIM_CR1_CEN, 0x3FU); // Enable timer
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// Set mode
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switch(mode) {
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case CLOCK_SOURCE_MODE_DISABLED:
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// No clock signal
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NVIC_DisableIRQ(EXTI0_IRQn);
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NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
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NVIC_DisableIRQ(TIM1_CC_IRQn);
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// Disable pulse if we were in the middle of it
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set_gpio_output(GPIOB, 14, false);
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set_gpio_output(GPIOB, 15, false);
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clock_source_mode = CLOCK_SOURCE_MODE_DISABLED;
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break;
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case CLOCK_SOURCE_MODE_FREE_RUNNING:
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// Clock signal is based on internal timer
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NVIC_DisableIRQ(EXTI0_IRQn);
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NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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clock_source_mode = CLOCK_SOURCE_MODE_FREE_RUNNING;
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break;
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case CLOCK_SOURCE_MODE_EXTERNAL_SYNC:
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// Clock signal is based on external timer
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NVIC_EnableIRQ(EXTI0_IRQn);
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NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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clock_source_mode = CLOCK_SOURCE_MODE_EXTERNAL_SYNC;
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break;
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default:
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puts("Unknown clock source mode: "); puth(mode); puts("\n");
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break;
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}
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} |